James's Resume
J. Patrick Crimm
pat.crimm@gmail.com
P.O. BOX 5311, Jackson, MS 39296, (802) 238-9340
EXPERIENCE: Electrical Engineer, December 2007 to July 2010
Applied Geo Technologies Inc. (AGT), 390 Industrial Road, Choctaw, MS 39350
• Lead Engineer responsible for Department of Defense (DoD) robotics products. Duties included:
• Led technology transfer of updated electronics system for manufacturing.
• Wrote work instructions and drove continuous product improvements.
• Administrator of Engineering Bill of Materials (EBOM), Engineering Change Proposals (ECP), Notice of Revision (NOR), Engineering Change Notices (ECN), Technical Bulletins, Statements of Work (SOW).
• Primary technical liaison to DoD Robotic Systems Joint Procurement Office (RS JPO) and Joint Robotics Repair Facilities (JRRF).
• Primary technical contact with suppliers for electronics.
• Successfully worked through obsolescence and logistics issues of product.
• Assembled Technology Data Package and completed technical writing of associated manuals, instructions, and troubleshooting guide.
• Led effort in collaboration with Schafer Corp. to upgrade SCALE robot operating system software from version 2 to version 3. This included testing, introduction of features for ease of manufacturing, and as liaison with RS JPO to incorporate customer requests into software upgrade.
• Assumed all R&D responsibilities for RF upgrade and assembled package (SOW requirements including Contract Data Requirement Lists (CDRL) resulting in an additional $215,000 contract for AGT.
• Developed internal test procedures and assisted Quality Dept. with acceptance procedures.
• Trained technicians in production and troubleshooting techniques.
Circuit Design Engineer, November 2005 to April 2007
ASICNorth, 100 Dorset St., Ste. 11, So. Burlington, VT 05403
• Sole responsibility for technology redesign (shrink) of serializer with phase / timing adjustment circuitry from 0.12 m to 0.09 m technologies. Duties included:
• Resizing and conversion to triple well utilizing Cadence Analogue Artist.
• Custom layout of analogue and fast DFF circuits consistent with ASIC methodology using Cadence Virtuoso suite.
• Redesign of custom clock drivers to reduce power consumption and extensive simulation for verification.
• Complete layout of serializer through power grid (M5) mixing IBM ASIC and custom ASIC cells constrained by a tight floorplan; full DRC and LVS.
• Other duties included providing HSPICE decks for measurements used to create Einstimer, Liberty and IBIS models for LVDS and other circuits.
Defect Characterization Engineer/Scientist, July 1998 to June 2002
IBM/CDI, 1000 River Street, Essex Junction, VT 05452
• Team leader for FEOL (defects / processes from substrate to contacts).
• Designed and debugged electrical tests for emerging technologies to 0.09 m.
• Monitored process and tool related defects and performed statistical analysis to increase yield and isolate defective tools and processes.
• Tracked and analyzed process changes and improvements.
• Automated data analysis to display trends and designed website for easy access.
• Research in defect cause and effect resulted in the recovery of a substantial amount of IBM hardware.
Employed as Contractor in Technology Development, gained experience in technology development, transfer, and manufacturing, and advanced consistently every year; hired permanently by IBM in 2000 as experienced engineer.
System Engineer, Summer 1997, Vermont Yankee Nuclear Power Corp.
• Assisted in update of fire prevention systems; ordering; work oversight.
Civil Engineer/Architect, Fall 1996, IBM Microelectronics Division
• Drove update of site electric CAD maps and tool hookups.
EDUCATION: Master of Science in Electrical Engineering, 2005 GPA: 3.3
University of Vermont, Burlington, Vermont
Major study in Analog/mixed signal design; Secondary: Semiconductor Physics.
Design projects and courses included:
Advanced Analog Design: Design of Operational Transconductance Amplifier for low noise and low power consumption using TSMC 0.25 CMOS.
Analog/mixed signal Design: Design and layout of analog elements (Modulator) for A/D Converter including Op-amps, Comparator, switches.
Design of clock synchronized PLL for 10.6 GHz transmitter using IBM SiGe BiCMOS 7WL 0.18 technology.
DRAM Design DSP Advanced Semiconductor Physics
Bachelor of Science in Electrical Engineering, 1998 GPA: 3.0
University of Vermont, Burlington, Vermont
Computer Engineering Option
TOOLS/ Cadence Design Suite, Spice, Spectre, VHDL, Verilog, Verilog_A, C, SAS,
PROGRAMMING: Matlab & DSP Toolkit, Mathematica, Mathcad, Tubecad, GYM.
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